Secrets of the Adat Optical Link

Alesis has never put details of the Adat optical link into the public domain. They are not available on their website nor in any of the manuals for their products or, as far as I am aware, are they in any of the manuals from any of the other companies which manufacture interfaces based on the Adat interface, or Adat Lite Pipe as some call it. The non-disclosure agreement that they ask people to sign is very restrictive and as such, is really not suitable for an educational establishment which exists to promote research and the dissemination of knowledge. So, in 1997, I decided to reverse engineer the Adat interface. Taking the original Adat we had purchased in the very early days, I discovered that the ADC's used were the Crystal Semiconductor CSCS5336 for which I had data sheets and better yet, they were in sockets. They were being used in slave mode, with no fsync pulse. This made it very simple to build a hardware emulator using 74HC logic ( two '166 shift registers, a '74 dual flip-flop and a bunch of gates, if you're interested) which could be used to put known data out through the Adat Optical Link. The shift register inputs were hooked up 16 switches, enabling each bit to be set to 1 or 0 independently. The results of this can be seen in the following image, which shows the Adat Optical Link data structure. What is shown here is the start of one block of eight samples with several different bits set in the first word;

Note that the long pulse at the start of the data stream on the Adat Optical Link is obviously the sync character, that the data is split up into cells containing nibbles which have 4 bits of data each, that data at 1 causes a transition, that at 0 does not, unless at the start of a cell, and that there is an empty cell after the sync character, which is presumably where the extra bits needed for the 20 bit models goes, though this has not been verified yet (does the sync character shrink in 24 bit mode to allow another four bit cell??). Psuedo-code for the Adat Optical Link might be written as follows;-


if {start of block} {
	transit
	stay stable for 11 clocks
	transit
	stay stable for 5 clocks
} else {
	for channel 0 to channel 7 {
		for nibble 0 to nibble 4 { 
			transit
			for data 0 to data 3 {
				if data = 1 {
					transit 
				}
			next data
			}
		next nibble
	} 
	next channel
}
end

Please note that if you are going to use this information about the Adat Optical Link for commercial purposes, you must get Alesis's permission and in any case you will probably want to use their IC's. Please also note, I take absolutely no responsibility for its accuracy or legal status, nor for any problems you may encounter if you try and apply it - the information is provided as-is, as a public service and without any warranty of any sort

Since I first put this site up in December 1999, I have located the patents related to the Adat interface and the Alesis recorder synchronisation connector, thanks to IBM's excellent patent server site.

The interface is described in US patent no. 5,297,181. It is basically as I have described it above, but the data frame is described as having 256 bit cells per sample period, of which 192 are allocated to data thus allowing for eight 24 bit channels or 12 sixteen bit channels (!). The code is actually as follows;
The data bits are split into 48 nibbles of 4 bits each, with an extra '1' added to the end of each nibble. These are transmitted using what is described as None Return to Zero Inverted (NRZI) modulation in which ones are represented by a transition and zeroes by the lack of a transition. This occupies 240 of the 256 bit cells. After the data, ten zeroes are transmitted as a sync character, then a '1' then 4 user bits and a final '1'

Strangely, much of the patent is taken up with circuit descriptions of what seems to be a perfectly normal phase lock loop clock extraction circuit and little in it seems at all new or probably even protectable - but I'm no lawyer, so please don't take my word for it!

European patent EP 0 621 976 B1 describes the 'sync' connector on the back of Adats. I won't attempt to do more than precis what is on the connector itself;

Connections on the Adat sync connector

The Midi connections allow recorders to talk to each other, communicating their locations in the chain, etc. and also allow for BRC control functions - all via midi system exclusive functions. The 48kHz clock enables sample accurate locking and the timecode allows the machines to be brought into time sync after they have started up. Once again, I find very little that is new in this, just a mass of circuit operation descriptions - very useful for understanding the way it works, but is it really original enough for patenting - if it really is, I should have applied for hundreds of patents!


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Last updated 20th. January 2000

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